Micro-Nano Electronics

  • Name:Yaoyao Ye
  • Title:Associate Professor
  • Office:Building of Microelectronics, Rm 418
  • Office Phone:+86-21-34204546-1041
  • Email:yeyaoyao@sjtu.edu.cn
  • Website:

Research Field

Integrated Circuit Electronic Design Automation, AI Chip Architecture, Heterogeneous Multi-Core Processor Architecture, On-Chip Network

Education

Ph.D. in Electronic and Computer Engineering, The Hong Kong University of Science and Technology, 2013;
B.S. in Eletronic Science and Technology, University of Science and Technology of China, 2008

Work experience

Nov. 2013-Mar. 2015, Research Engineer, Huawei Technologies Co., Ltd.
Apr. 2015- Nov. 2020, Assistant Professor, Department of Micro/Nano Electronics, Shanghai Jiao Tong University
Dec. 2020, Associate Professor, Department of Micro/Nano Electronics, Shanghai Jiao Tong University

Research

Dr. Ye has published more than 50 papers in international journals such as IEEE TCAD, IEEE TVLSI and international academic conferences. She serves as TPC member of important international academic conferences in the field of EDA, such as ASP-DAC 2024, DATE 2023, NOCS 2023, NOCS 2022, ASP-DAC 2021, ASP-DAC 2020, ASP-DAC 2019, ASP-DAC 2017, ASP-DAC 2016, GLSVLSI 2017, etc. She is the project leader of two projects funded by the National Natural Science Foundation of China.

Awards and Honors

Recipient of Shanghai Sailing Program for Young Scientific Talents (2016)

Teaching

ICE2301 Signals and Systems (A)

Publications

Referred Journal Publications:
[1]Guanglong Li and Yaoyao Ye*, "HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN Accelerators," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 3, pp. 812-825, March 2024.
[2]Jinming Zhang, Xi Fan, Yaoyao Ye*, Xuyan Wang, Guojie Xiong, Xianglun Leng, Ningyi Xu, Yong Lian and Guanghui He*, "INDM: Chiplet-Based Interconnect Network and Dataflow Mapping for DNN Accelerators," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 4, pp. 1107-1120, April 2024.
[3]Jing Wang and Yaoyao Ye*, “Ant Colony Optimization-Based Thermal-Aware Adaptive Routing Mechanism for Optical NoCs”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 40, no. 9, pp. 1836-1849, Sept. 2021.
[4]Wenfei Zhang, Yaoyao Ye*, “A Table-Free Approximate Q-Learning Based ThermalAware Adaptive Routing for Optical NoCs”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 40, no. 1, pp. 199-203, Jan. 2021.
[5]Renjie Yao, Yaoyao Ye*, “Towards a High-Performance and Low-Loss Clos-Benes Based Optical Network-on-Chip Architecture”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 12, pp. 4695-4706, Dec. 2020.
[6]Yaoyao Ye*, Wenfei Zhang, Weichen Liu, “Thermal-Aware Design and Simulation Approach for Optical NoCs”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 10, pp. 2384-2395, Oct. 2020.
[7]Yaoyao Ye*, Zhe Zhang, “A Thermal-Sensitive Design of a 3D Torus-Based Optical NoC Architecture”, Integration, the VLSI journal, 2019.
[8]Zhe Zhang, Yaoyao Ye*, “A Learning-Based Thermal-Sensitive Power Optimization Approach for Optical NoC”, in ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 14, no 2, May 2018.
[9]Mengquan Li, Weichen Liu*, Nan Guan, Yiyuan Xie, Yaoyao Ye, “Hardware-Software Collaborative Thermal Sensing in Optical Network-on-Chip Based Manycore Systems”, in ACM Transactions on Embedded Computing Systems, Article 118, November 2019.
[10]Hengyang Zhao, Qi Hua, Hai-Bao Chen, Yaoyao Ye, Hai Wang, Sheldon X.-D. Tan, and Esteban Tlelo-Cuautle. “Thermal-Sensor-Based Occupancy Detection for Smart Buildings Using Machine-Learning Methods”, in ACM Transactions on Design Automation of Electronic Systems, 23, 4, Article 54, June 2018.
[11]Yaoyao Ye, Zhehui Wang, Peng Yang, Jiang Xu, Xiaowen Wu, Xuan Wang, Mahdi Nikdast, Zhe Wang, Luan Huu Kinh Duong, “System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 11, pp. 1718-1731, November 2014.
[12]Yaoyao Ye, Jiang Xu, Baihan Huang, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu, and Zhe Wang, “3D Mesh-based Optical Network-on-Chip for Multiprocessor System-on-Chip”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no.4, pp. 584-596, April 2013.
[13]Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, and Weichen Liu, “System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip”, in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 21, no. 2, pp. 292-305, February 2013.
[14]Yaoyao Ye, Jiang Xu, XiaowenWu, Wei Zhang, Weichen Liu, and Mahdi Nikdast, “A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip”, in ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 8, no 1, February 2012.

Referred Conference Publications:
[1]Yihao Liu, Yaoyao Ye*, “An Efficient Branch-and-Bound Routing Algorithm for Optical NoCs”, 29th Asia and South Pacific Design Automation Conference (ASP-DAC), Incheon, Korea, Republic of, 2024, pp. 860-865.
[2]Hao Chen, Xuyan Wang, Jinming Zhang, Xiao Han, Siqi Cai, Yaoyao Ye* and Guanghui He*, "MEIN: A Multicast-Efficient Interconnect Network for Multi-Chiplet DNN Accelerators," accepted by the IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, May 19-22, 2024.
[3]Yaoyao Ye, Zixuan Liu, Jungan Liu, Li Jiang, “ASDR: An Application-Specific Deadlock-Free Routing for Chiplet-Based Systems”, in Proceedings of the 16th IEEE/ACM International Workshop on Network on Chip Architectures (NoCArc), Oct. 28, 2023.
[4]Ke Wu, Yaoyao Ye*, "Q-Learning Based Bi-Objective Deadlock-Free Routing Optimization for Optical NoCs," in Proceedings of the 15th IEEE/ACM International Workshop on Network on Chip Architectures (NoCArc), Chicago, IL, USA, Oct. 02, 2022.
[5]Xi Fan, Xuyan Wang, Yaoyao Ye*, Xianglun Leng, Ningyi Xu, Guanghui He*, “CCASM: A Computation- and Communication-Aware Scheduling and Mapping Algorithm for NoC-Based DNN Accelerators,” IEEE 14th International Conference on ASIC (ASICON), Kunming, China, pp. 1-4, Oct. 2021.
[6]Wenfei Zhang, Yaoyao Ye*, “An Approximate Thermal-Aware Q-Routing for Optical NoCs”, PHOTONICS 2019, in conjunction with International Conference for High Performance Computing, Networking, Storage, and Analysis (SC 2019), Denver, USA, November 18th, 2019.
[7]Renjie Yao, Yaoyao Ye*, Weichen Liu, “Design of a Hierarchical Clos-Benes Optical Network-on-Chip Architecture”, IEEE Computer Society Annual Symposium on VLSI, Miami, Florida, U.S.A., July 15-17, 2019.
[8]Yaoyao Ye, Taeyoung Kim, Haibao Chen, Hai Wang, Esteban Tlelo-Cuautle and Sheldon X.-D. Tan, “Comprehensive Detection of Counterfeit ICs Via On-Chip Sensor and Post-Fabrication Authentication Policy”, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), June 2017, Italy.
[9]Kang Yao, Yaoyao Ye*, Jiang Xu and Sudeep Pasricha, “Thermal-Sensitive Design and Power Optimization for a 3D Torus-Based Optical NoC”, International Conference on Computer Aided Design (ICCAD), November 13-16, 2017, Irvine Marriott, Irvine, CA.
[10]Zhe Zhang, Yaoyao Ye, Weichen Liu, “A Learning-Based Thermal-Sensitive Routing for Power Optimization of Optical NoCs”, 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), October 4-5, 2018, Torino, Italy. (Poster)
[11]Wenyang Liu, Weichen Liu, Mengquan Li, Peng Chen, Lei Yang, Chunhua Xiao, Yaoyao Ye, “Fine-Grained Task-Level Parallel and Low Power H.264 Decoding in Multi-Core Systems”, IEEE 24th International Conference on Parallel and Distributed Systems (ICPADS), Singapore, 2018, pp. 307-314.
[12]Yanting Huang, Weichen Liu, Mengquan Li, Peng Chen, Lei Yang, Chunhua Xiao, Yaoyao Ye, “User Experience-Enhanced and Energy-Efficient Task Scheduling on Heterogeneous Multi-Core Mobile Systems”, IEEE 24th International Conference on Parallel and Distributed Systems (ICPADS), Singapore, 2018, pp. 283-290.
[13]Mengquan Li, Weichen Liu, Lei Yang, Yiyuan Xie, Yaoyao Ye, Nan Guan, “Work-in-Progress: Communication Optimization for Thermal Reliable Optical Network-on-Chip”, 2018 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Turin, 2018, pp. 1-2.
[14]Yaoyao Ye, Xiaowen Wu, Jiang Xu, Mahdi Nikdast, Zhehui Wang, Xuan Wang, and ZheWang, “System-Level Analysis of Mesh-based Hybrid Optical-Electronic Network-on-Chip”, the 2013 IEEE International Symposium on Circuits and Systems, Beijing, China, May 2013. (Invited)
[15]Yaoyao Ye, Xiaowen Wu, Jiang Xu, Wei Zhang, Mahdi Nikdast, Xuan Wang, Zhehui Wang, and Zhe Wang, “Holistic Comparison of Optical Routers for Chip Multiprocessors”, IEEE International Conference on Anti-Counterfeiting, Security and Identification, Taipei, Taiwan, August 2012. (Invited)
[16]Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang, Zhehui Wang, and Zhe Wang, “Thermal Analysis for 3D Optical Network-on-Chip Based on a Novel Low-Cost 6x6 Optical Router”, IEEE Optical Interconnects Conference, Santa Fe, New Mexico, USA, May 2012.
[17]Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu, “Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip”, IEEE Computer Society Annual Symposium on VLSI, Chennai, India, July 2011.
[18]Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Kwai Hung Mo, Yuan Xie, “3D Optical NoC for MPSoC”, IEEE International 3D System Integration Conference, San Francisco, USA, September 2009.
[19]Qi Hua, Haibao Chen, Yaoyao Ye and Sheldon X.-D. Tan, “Occupancy Detection in Smart Buildings Using Support Vector Regression Method”, 2016 8th International Conference on Intelligent Human-Machine Systems and Cybernetics (IHMSC), Hangzhou, 2016, pp. 77-80.
[20]Weichen Liu, Zonghua Gu, Yaoyao Ye, “Efficient SAT-based application mapping and scheduling on multiprocessor systems for throughput maximization”, in Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2015 International Conference on , vol., no., pp.127-136, 4-9 Oct. 2015.
[21]Jie Dai, Weichen Liu, Xiaohao Lin, Yaoyao Ye, Chunming Xiao, Kaijie Wu, Qingfeng Zhuge, Sha, E.H.M., “User Experience Enhanced Task Scheduling and Processor Frequency Scaling for Energy-Sensitive Mobile Devices”, in High Performance Computing and Communications (HPCC), 2015 IEEE 7th International Symposium on Cyberspace Safety and Security (CSS), 2015 IEEE 12th International Conference on Embedded Software and Systems (ICESS), 2015 IEEE 17th International Conference on , vol., no., pp.941-944, 24-26 Aug. 2015.
[22]Zhehui Wang, Jiang Xu, Peng Yang, Xuan Wang, Zhe Wang, Luan H.K. Duong, Zhifei Wang, Haoran Li, Rafael K.V. Maeda, Xiaowen Wu, Yaoyao Ye, Qinfen Hao, “Alleviate Chip I/O Pin Constraints for Multicore Processors through Optical Interconnects”, Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, January 2015.

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