Dr. Sun's research area is low-power, high-performance, and variation-tolerant VLSI circuit and system design with emerging nanoscale transistor and memory technologies. She also has interests in 3D integration design and applications of machine-learning in VLSI.

Dr. Sun received the B.E. degree in Microelectronics from Shanghai Jiao Tong University in 2009. She got the Ph.D. degree in Electronic and Computer Engineering from the Hong Kong University of Science and Technology in 2015.

2019.01-Present Associate Professor, Department of Micro-Nano Electronics, Shanghai Jiao Tong University.
2015.10-2018.12 Assistant Professor, Department of Micro-Nano Electronics, Shanghai Jiao Tong University.

Dr. Sun received the Best Paper Award – First Place in the IEEE 26th International Conference on Microelectronics in 2014. She currently serves on the editorial board of the Microelectronics Journal.

ES26030 (Postgraduate Course) -- Advanced Digital Integrated Circuits Design
ES26047 (Postgraduate Course) -- Advanced Technologies of Integrated Circuit Design
MR310 (Undergraduate Course) -- Digital Integrated Circuits
MR332 (Undergraduate Course) -- Frontier Lectures on Micro-Nano Electronics Science and Technology

Journal Publications:
[1] Y. Sun, J. Gu, W. He, Q. Wang, N. Jing, Z. Mao, W. Qian, and L. Jiang, “Energy-efficient nonvolatile SRAM design based on resistive switching multi-level cells,” IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 66, No. 5, pp. 753-757, May 2019.
[2] Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, “Metallic-CN-removal-tolerant high-yield six-CNMOSFET SRAM cell for carbon-based embedded memory,” IEEE Transactions on Electron Devices (TED), Vol. 65, No. 3, pp. 1230-1238, March 2018.
[3] C. Wang, Y. Sun, S. Hu, L. Jiang, W. Qian, “Variation-aware global placement for improving timing-yield of carbon-nanotube field effect transistor circuit,” ACM Transactions on Design Automation of Electronic Systems, Vol. 23, No. 4, pp. 1-27, June 2018.
[4] Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, “High-yield and robust 9T SRAM cell tolerant to removal of metallic carbon nanotubes,” IEEE Transactions on Device and Materials Reliability (TDMR), Vol. 17, No. 1, pp. 20-31, March 2017.
[5] Y. Sun, W. He, Z. Mao, and V. Kursun, “Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic,” Microelectronics Journal (MEJ), Vol. 62, pp. 12-20, February 2017.
[6] Y. Sun, H. Jiao, and V. Kursun, “A novel robust and low-leakage SRAM cell with nine carbon nanotube transistors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 9, pp. 1729-1739, September 2015.
[7] Y. Sun and V. Kursun, “Carbon nanotubes blowing new life into NP dynamic CMOS circuits,” IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 61, No. 2, pp. 420-428, February 2014.
[8] Y. Sun and V. Kursun, “N-type carbon-nanotube MOSFET device profile optimization for very large scale integration,” Transactions on Electrical and Electronic Materials, Vol. 12, No. 2, pp. 43-50, April 2011. (invited)
[9] W. Jin, W. He, J. Jiang, H. Huang, X. Zhao, Y. Sun, X. Chen, and N. Jing, “A 0.33V 2.5μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130nm CMOS,” Integration, the VLSI Journal, Vol. 58, pp. 27-34, February 2017.

Conference Publication:
[1] Y. Lu, Y. Sun*, W. He, and Z. Mao, “A novel memristor-reusable mapping methodology of in-memory logic implementation for high area-efficiency,” Proceedings of the IEEE/ACM International Symposium on Nanoscale Architecture, June 2019.
[2] Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, “Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes,” Proceedings of the IEEE International Conference on Electronics, Information, and Communication (ICEIC), January 2019.
[3] P. Ji, J. Gao, W. Xu, Y. Sun, W. He, and H. Wu, “Electronic-photonic integrated circuit design and crosstalk modeling for a high density multi-lane MZM array,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2018.
[4] Y. Sun, Wei. He, Z. Mao, H. Jiao, and V. Kursun, “Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors,” Proceedings of the IEEE International Conference on ASIC (ASICON), pp. 908-911, October 2017. (invited)
[5] L. Chen, Y. Sun*, and W. He, “Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme,” Proceedings of the IEEE International Conference on ASIC (ASICON), pp. 916-919, October 2017. (invited)
[6] W. Xu, J. Gao, P. Ji, Y. Sun, W. He, and H. Wu, “A PAM-4 optical receiver based on a silicon photonic quantizer,” IEEE International Conference on Group IV Photonics (GFP), pp. 117-118, August 2017.
[7] J. Gao, Y. Sun, W. He, and H. Wu, “A cross-layer multi-physics design flow for electronic-photonic integrated circuits,” IEEE Photonics Conference (IPC), pp. 230-231, January 2017.
[8] N. Jing, T. Li, Z. Zhao, W. Jin, Y. Sun, W. He, and Z. Mao, “Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory,” International Conference on Field-Programmable Technology (FPT), pp. 233-236, December 2016.
[9] Y. Sun and V. Kursun, “Carbon-based sleep switch dynamic logic circuits with variable strength keeper for lower-leakage currents and higher-speed,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2720-2723, May 2015.
[10] Y. Sun, H. Jiao, and V. Kursun, “Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins,” Proceedings of the IEEE International Conference on Microelectronics (ICM), pp. 164-167, December 2014. (Best paper award – first place)
[11] Y. Sun and V. Kursun, “A comparison of high-frequency 32-bit dynamic adders with conventional silicon and novel carbon nanotube transistor technologies,” Proceedings of the IEEE International SoC Design Conference (ISOCC), pp. 39-42, November 2013.
[12] Y. Sun and V. Kursun, “Low-power and compact NP dynamic CMOS adder with 16nm carbon nanotube transistors,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2119-2122, May 2013.
[13] Y. Sun and V. Kursun, “NP dynamic CMOS resurrection with carbon nanotube field effect transistors,” Proceedings of the IEEE International SoC Design Conference, pp. 13-16, November 2012.
[14] Y. Sun and V. Kursun, “Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm p-channel MOSFETs,” Proceedings of the IEEE International Conference on VLSI and System-on-Chip (VLSI-SoC), pp. 226-231, October 2011.
[15] Y. Sun and V. Kursun, “Substrate bias considerations for low leakage 16nm p-channel carbon nanotube transistors,” Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, August 2011.
[16] Y. Sun and V. Kursun, “Uniform diameter and pitch co-design of 16nm n-type carbon nanotube channel arrays for VLSI,” Proceedings of the IEEE International Asia Symposium on Quality Electronic Design (ASQED), pp. 211-216, July 2011.
[17] Y. Sun and V. Kursun, “Leakage current and bottom gate voltage considerations in developing maximum performance 16nm n-channel carbon nanotube transistors,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2513-2516, May 2011.
[18] Y. Sun and V. Kursun, “Physical parametric analysis of 16nm n-channel carbon-nanotube transistors for manufacturability,” Proceedings of the IEEE International Conference on Microelectronics, pp. 28-31, December 2010.
[19] Y. Sun and V. Kursun, “16nm p-type carbon nanotube MOSFET device profile optimization for high-speed,” Proceedings of the IEEE International SoC Design Conference, pp. 260-263, November 2010.