Recently, Professor Jianjun Zhou's group in the Department of Micro and Nano Electronics of the School of Electronic Information and Electrical Engineering published the results of analog-to-digital converter (ADC) chip in the IEEE Journal of Solid-State Circuits (IEEE JSSC).

The IEEE Journal of Solid-State Circuits is one of the highest level journals in the international integrated circuit field, aiming to publish the latest technical advances and record results in the field of integrated circuit design, representing the highest level of current technology in the industry.

The research focuses on solving the design challenges faced by ADCs when integrating input buffers, revealing the mechanism of ADC inter-symbol crosstalk generation and its impact on ADC accuracy, and proposing dynamic level-shifting techniques and sampling error correction techniques, thus achieving improved linearity of high-performance ADCs with on-chip integrated buffers.

The ADC chip was fabricated in a CMOS process. It achieves 84.2dB SNDR and 97.3dB SFDR at a sampling rate of 60MS/s with a bandwidth of 5MHz. which is among the best in the literature for SAR ADCs with integrated input buffers (FoMW of 60.6 fJ/conv.-step and FoMS of 172.1 dB). In addition, the chip is designed with digitally assisted calibration techniques, and chip reliability issues such as ESD protection are also taken into consideration.

PhD student Yuekang Guo is the first author of the paper, and Prof. Jing Jin is the corresponding author. The authors are all from the Analog/RF IC Design Center, Department of Micro and Nano Electronics, Shanghai Jiao Tong University. The research was funded by the National Natural Science Foundation of China.

Paper Link: https://ieeexplore.ieee.org/document/9810848